//////////////////////////////////////////////////////////////////////
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////  CFBaseLowLevel.v                                            ////
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////                                                              ////
////  This file is part of the "Pico E12" project                 ////
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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005, Pico Computing, INC.                     ////
//// http://www.picocomputing.com                                 ////
////                                                              ////
////////////////////////////////////////////////////////////////////JF

//This is an absurd way to handle inputs and outputs. As of this writing certain pieces of software fail to implement 
//tristate buffers properly on the Virtex-4. This file serves as a work-around.

//All IOBuffers and PAD wires are defined in the file.

//CF Input
input CLOCK1_PAD;
input CLOCK2_PAD;
input CLOCKY9_PAD;
output DCM_KEEPER_PAD;
inout CE1_PAD;
inout CE2_PAD;
inout REG_PAD;
inout IORD_PAD;
inout IOWR_PAD;
inout OE_PAD;
inout WE_PAD;

//CF Output
inout READY_PAD;
inout WAIT_PAD;
inout WP_IOIS16_PAD;
inout INPACK_PAD;
inout BVD1_PAD;
inout BVD2_PAD;

//CF Control
output MASTEREN_PAD;
output ADDRESSDIR_PAD;
output CTRLDIR_PAD;
output DATADIRH_PAD;
output DATADIRL_PAD;

//CF Bi-directional databus
inout D_PAD0;                            
inout D_PAD1;
inout D_PAD2;
inout D_PAD3;
inout D_PAD4;
inout D_PAD5;
inout D_PAD6;
inout D_PAD7;
inout D_PAD8;
inout D_PAD9;
inout D_PAD10;
inout D_PAD11;
inout D_PAD12;
inout D_PAD13;
inout D_PAD14;
inout D_PAD15;

//CF Addressbus
inout A_PAD0;
inout A_PAD1;
inout A_PAD2;
inout A_PAD3;
inout A_PAD4;
inout A_PAD5;
inout A_PAD6;
inout A_PAD7;
inout A_PAD8;
inout A_PAD9;
inout A_PAD10;

//Flash Control Lines

output            FLASH_CE_PAD;
output            FLASH_OE_PAD;
output            FLASH_WE_PAD;
output            FLASH_WP_PAD;
output            FLASH_RESET_PAD;
output            FLASH_BYTE_PAD;
input             FLASH_BUSY_PAD;

inout             FLASHD_PAD0;
inout             FLASHD_PAD1;
inout             FLASHD_PAD2;
inout             FLASHD_PAD3;
inout             FLASHD_PAD4;
inout             FLASHD_PAD5;
inout             FLASHD_PAD6;
inout             FLASHD_PAD7;
inout             FLASHD_PAD8;
inout             FLASHD_PAD9;
inout             FLASHD_PAD10;
inout             FLASHD_PAD11;
inout             FLASHD_PAD12;
inout             FLASHD_PAD13;
inout             FLASHD_PAD14;
inout             FLASHD_PAD15;
inout             FLASHA_PAD0;

inout             FLASHA_PAD1;
inout             FLASHA_PAD2;
inout             FLASHA_PAD3;
inout             FLASHA_PAD4;
inout             FLASHA_PAD5;
inout             FLASHA_PAD6;
inout             FLASHA_PAD7;
inout             FLASHA_PAD8;
inout             FLASHA_PAD9;
inout             FLASHA_PAD10;                                     
inout             FLASHA_PAD11;
inout             FLASHA_PAD12;
inout             FLASHA_PAD13;
inout             FLASHA_PAD14;
inout             FLASHA_PAD15;
inout             FLASHA_PAD16;
inout             FLASHA_PAD17;
inout             FLASHA_PAD18;
inout             FLASHA_PAD19; 
inout             FLASHA_PAD20;                                       
inout             FLASHA_PAD21;
inout             FLASHA_PAD22;
inout             FLASHA_PAD23;
inout             FLASHA_PAD24;
inout             FLASHA_PAD25;

output            CPLD_PEEKABOO_PAD;
output            CPLD_RELOAD_PAD; 

output            JTAG_LOOPBACK_TCK_PAD;
output            JTAG_LOOPBACK_TDI_PAD;
input             JTAG_LOOPBACK_TDO_PAD;
output            JTAG_LOOPBACK_TMS_PAD;

`ifdef ENABLE_GPIO_PADS
inout             GPIO_PAD1;
inout             GPIO_PAD2;
inout             GPIO_PAD3;
inout             GPIO_PAD4;
`endif

`ifdef ENABLE_ETH
 output ETHER_GTX_CLK;
 input  ETHER_RX_CLK;
 input  ETHER_RX_CTL;
 input  ETHER_RX_ER;
 input  [7:0] ETHER_RX;
 input  ETHER_TX_CLK;
 output ETHER_TX_EN;
 output ETHER_TX_ER;
 output [7:0] ETHER_TX;
 `endif //ENABLE_ETH

 `ifdef ENABLE_MDIO_LOW_LEVEL
 output ETHER_25MHZ_PAD;
 output ETHER_COMA_PAD;
 output ETHER_MDC_PAD;
 inout  ETHER_MDIO_PAD;
 output ETHER_RESET_PAD;
 `endif


//---------------------------------------------Raw Pad Wires---------------------------------------------------//
wire              CLOCK1_PAD;
wire              CLOCK2_PAD;
wire              CLOCKY9_PAD;
wire              DCM_KEEPER_PAD;
wire              CE1_PAD;
wire              CE2_PAD;
wire              REG_PAD;
wire              IORD_PAD;
wire              IOWR_PAD;
wire              OE_PAD;
wire              WE_PAD;                            
wire              READY_PAD;
wire              WAIT_PAD; 
wire              WP_IOIS16_PAD; 
wire              INPACK_PAD;
wire              BVD1_PAD;
wire              BVD2_PAD;                               
wire              MASTEREN_PAD;
wire              ADDRESSDIR_PAD;  
wire              CTRLDIR_PAD;  
wire              DATADIRH_PAD;
wire              DATADIRL_PAD;
wire              D_PAD0;
wire              D_PAD1;
wire              D_PAD2;
wire              D_PAD3;
wire              D_PAD4;
wire              D_PAD5;
wire              D_PAD6;
wire              D_PAD7;
wire              D_PAD8;
wire              D_PAD9;
wire              D_PAD10;
wire              D_PAD11;
wire              D_PAD12;
wire              D_PAD13;
wire              D_PAD14;
wire              D_PAD15;
wire              A_PAD0;
wire              A_PAD1;
wire              A_PAD2;
wire              A_PAD3;
wire              A_PAD4;
wire              A_PAD5;
wire              A_PAD6;
wire              A_PAD7;
wire              A_PAD8;
wire              A_PAD9;
wire              A_PAD10;

wire              FLASH_CE_PAD;
wire              FLASH_OE_PAD;
wire              FLASH_WE_PAD;
wire              FLASH_WP_PAD;
wire              FLASH_RESET_PAD;
wire              FLASH_BYTE_PAD;
wire              FLASH_BUSY_PAD;

wire              FLASHD_PAD0;
wire              FLASHD_PAD1;
wire              FLASHD_PAD2;
wire              FLASHD_PAD3;
wire              FLASHD_PAD4;
wire              FLASHD_PAD5;
wire              FLASHD_PAD6;
wire              FLASHD_PAD7;
wire              FLASHD_PAD8;
wire              FLASHD_PAD9;
wire              FLASHD_PAD10;
wire              FLASHD_PAD11;
wire              FLASHD_PAD12;
wire              FLASHD_PAD13;
wire              FLASHD_PAD14;
wire              FLASHD_PAD15;

wire              FLASHA_PAD0;
wire              FLASHA_PAD1;
wire              FLASHA_PAD2;
wire              FLASHA_PAD3;
wire              FLASHA_PAD4;
wire              FLASHA_PAD5;
wire              FLASHA_PAD6;
wire              FLASHA_PAD7;
wire              FLASHA_PAD8;
wire              FLASHA_PAD9;
wire              FLASHA_PAD10;
wire              FLASHA_PAD11;
wire              FLASHA_PAD12;
wire              FLASHA_PAD13;
wire              FLASHA_PAD14;
wire              FLASHA_PAD15;
wire              FLASHA_PAD16;
wire              FLASHA_PAD17;
wire              FLASHA_PAD18;
wire              FLASHA_PAD19; 
wire              FLASHA_PAD20;
wire              FLASHA_PAD21;
wire              FLASHA_PAD22;
wire              FLASHA_PAD23;
wire              FLASHA_PAD24;
wire              FLASHA_PAD25;

wire              CPLD_PEEKABOO_PAD;
wire              CPLD_RELOAD_PAD;

wire              JTAG_LOOPBACK_TCK_PAD;
wire              JTAG_LOOPBACK_TDI_PAD;
wire              JTAG_LOOPBACK_TDO_PAD;
wire              JTAG_LOOPBACK_TMS_PAD;

`ifdef ENABLE_GPIO_PADS
wire              GPIO_PAD1;
wire              GPIO_PAD2;
wire              GPIO_PAD3;
wire              GPIO_PAD4;
`endif

`ifdef ENABLE_ETH
 wire       ETHER_GTX_CLK;
 wire       ETHER_RX_CLK;
 wire       ETHER_RX_CTL;
 wire       ETHER_RX_ER;
 wire [7:0] ETHER_RX;
 wire       ETHER_TX_CLK;
 wire       ETHER_TX_EN;
 wire       ETHER_TX_ER;
 wire [7:0] ETHER_TX;
`endif //ENABLE_ETH

`ifdef ENABLE_MDIO_LOW_LEVEL
wire       ETHER_25MHZ;
wire       ETHER_COMA;
wire       ETHER_MDC;
wire       ETHER_MDIO_I;
wire       ETHER_MDIO_O;
wire       ETHER_MDIO_T;
wire       ETHER_RESET;
`endif //ENABLE_MDIO_LOW_LEVEL


//------------------------------------------RAW IOB Primitives----------------------------------------------//
//----Direction Inverters----//
wire              nCTRLDIR;
wire              nADDRESSDIR;

INV nCTRLDIR_INV(.I(CTRLDIR), .O(nCTRLDIR));
INV nADDRESSDIR_INV(.I(ADDRESSDIR), .O(nADDRESSDIR));


//Unused Signals in CFBase (used when reversing the databusses)
wire              CE1_IN;
wire              CE2_IN;
wire              REG_IN;
wire              IORD_IN;
wire              IOWR_IN;
wire              OE_IN; 
wire              WE_IN;  

wire              READY_OUT;
wire              WAIT_OUT;
wire              WP_IOIS16_OUT;
wire              INPACK_OUT;
wire              BVD1_OUT;
wire              BVD2_OUT;

wire              [10:0]A_IN;    


//----------Inputs-----------//
IBUFG CLOCK1_BUFG(.I(CLOCK1_PAD), .O(CLOCK1));
//synthesis attribute LOC of CLOCK1_PAD is "Y12"
//synthesis attribute IOSTANDARD of CLOCK1_BUFG is "LVTTL"

IBUFG CLOCK2_BUFG(.I(CLOCK2_PAD), .O(CLOCK2));
//synthesis attribute LOC of CLOCK2_PAD is "W11"
//synthesis attribute IOSTANDARD of CLOCK2_BUFG is "LVTTL"

IBUFG CLOCKY9_BUFG(.I(CLOCKY9_PAD), .O(CLOCKY9));
//synthesis attribute LOC of CLOCKY9_PAD is "Y9"
//synthesis attribute IOSTANDARD of CLOCKY9_BUFG is "LVTTL"
//synthesis attribute PULLDOWN

OBUF DCM_KEEPER_BUF(.O(DCM_KEEPER_PAD), .I(DCM_KEEPER));
//synthesis attribute LOC of DCM_KEEPER_PAD is "B10"
//synthesis attribute IOSTANDARD of DCM_KEEPER_BUF is "LVCMOS25"
//synthesis attribute DRIVE of DCM_KEEPER_BUF is "2"

IOBUF CE1_BUF(.IO(CE1_PAD), .O(CE1), .I(CE1_IN), .T(nADDRESSDIR));
//synthesis attribute LOC of CE1_PAD is "T6"
//synthesis attribute IOSTANDARD of CE1_BUF is "LVTTL"
//synthesis attribute DRIVE of CE1_BUF is "12"
//synthesis attribute SLEW of CE1_BUF is "FAST"

IOBUF CE2_BUF(.IO(CE2_PAD), .O(CE2), .I(CE2_IN), .T(nADDRESSDIR));
//synthesis attribute LOC of CE2_PAD is "U4"
//synthesis attribute IOSTANDARD of CE2_BUF is "LVTTL"
//synthesis attribute DRIVE of CE2_BUF is "12"
//synthesis attribute SLEW of CE2_BUF is "FAST"

IOBUF REG_BUF(.IO(REG_PAD), .O(REG), .I(REG_IN), .T(nADDRESSDIR));
//synthesis attribute LOC of REG_PAD is "T2"
//synthesis attribute IOSTANDARD of REG_BUF is "LVTTL"
//synthesis attribute DRIVE of REG_BUF is "12"
//synthesis attribute SLEW of REG_BUF is "FAST"

IOBUF IORD_BUF(.IO(IORD_PAD), .O(IORD), .I(IORD_IN), .T(nADDRESSDIR));
//synthesis attribute LOC of IORD_PAD is "W3"
//synthesis attribute IOSTANDARD of IORD_BUF is "LVTTL"
//synthesis attribute DRIVE of IORD_BUF is "24"
//synthesis attribute SLEW of IORD_BUF is "FAST"

IOBUF IOWR_BUF(.IO(IOWR_PAD), .O(IOWR), .I(IOWR_IN), .T(nADDRESSDIR));
//synthesis attribute LOC of IOWR_PAD is "U5"
//synthesis attribute IOSTANDARD of IOWR_BUF is "LVTTL"
//synthesis attribute DRIVE of IOWR_BUF is "24"
//synthesis attribute SLEW of IOWR_BUF is "FAST"

IOBUF OE_BUF(.IO(OE_PAD), .O(OE), .I(OE_IN), .T(nADDRESSDIR));
//synthesis attribute LOC of OE_PAD is "V4"
//synthesis attribute IOSTANDARD of OE_BUF is "LVTTL"
//synthesis attribute DRIVE of OE_BUF is "12"
//synthesis attribute SLEW of OE_BUF is "FAST"

IOBUF WE_BUF(.IO(WE_PAD), .O(WE), .I(WE_IN), .T(nADDRESSDIR));
//synthesis attribute LOC of WE_PAD is "U3"
//synthesis attribute IOSTANDARD of WE_BUF is "LVTTL"
//synthesis attribute DRIVE of WE_BUF is "24"
//synthesis attribute SLEW of WE_BUF is "FAST"


//----------Outputs----------//
IOBUF READY_BUF(.IO(READY_PAD), .I(READY), .O(READY_OUT), .T(nCTRLDIR));
//synthesis attribute LOC of READY_PAD is "W6"
//synthesis attribute IOSTANDARD of READY_BUF is "LVTTL"
//synthesis attribute DRIVE of READY_BUF is "12"
//synthesis attribute SLEW of READY_BUF is "FAST"

IOBUF WAIT_BUF(.IO(WAIT_PAD), .I(WAIT), .O(WAIT_OUT), .T(nCTRLDIR));
//IOBUF WAIT_BUF(.IO(WAIT_PAD), .I(1'b1), .O(WAIT_OUT), .T(nCTRLDIR));
//synthesis attribute LOC of WAIT_PAD is "W8"
//synthesis attribute IOSTANDARD of WAIT_BUF is "LVTTL"
//synthesis attribute DRIVE of WAIT_BUF is "12"
//synthesis attribute SLEW of WAIT_BUF is "FAST"

IOBUF WP_IOIS16_BUF(.IO(WP_IOIS16_PAD), .O(WP_IOIS16_OUT), .T(nCTRLDIR), .I(WP_IOIS16));
//synthesis attribute LOC of WP_IOIS16_PAD is "Y5"
//synthesis attribute IOSTANDARD of WP_IOIS16_BUF is "LVTTL"
//synthesis attribute DRIVE of WP_IOIS16_BUF is "12"
//synthesis attribute SLEW of WP_IOIS6_BUF is "FAST"

IOBUF INPACK_BUF(.IO(INPACK_PAD), .I(INPACK), .O(INPACK_OUT), .T(nCTRLDIR));
//synthesis attribute LOC of INPACK_PAD is "Y6"
//synthesis attribute IOSTANDARD of INPACK_BUF is "LVTTL"
//synthesis attribute DRIVE of INPACK_BUF is "12"
//synthesis attribute SLEW of INPACK_BUF is "FAST"

IOBUF BVD1_BUF(.IO(BVD1_PAD), .I(BVD1), .O(BVD1_OUT), .T(nCTRLDIR));
//synthesis attribute LOC of BVD1_PAD is "Y7"
//synthesis attribute IOSTANDARD of BVD1_BUF is "LVTTL"
//synthesis attribute DRIVE of BVD1_BUF is "12"
//synthesis attribute SLEW of BVD1_BUF is "FAST"

IOBUF BVD2_BUF(.IO(BVD2_PAD), .I(BVD2), .O(BVD2_OUT), .T(nCTRLDIR));
//synthesis attribute LOC of BVD2_PAD is "W7"
//synthesis attribute IOSTANDARD of BVD2_BUF is "LVTTL"
//synthesis attribute DRIVE of BVD2_BUF is "12"
//synthesis attribute SLEW of BVD2_BUF is "FAST"


//-------High Speed Databus Interface Direction Control and Master Enable--------//
OBUF MASTEREN_BUF(.O(MASTEREN_PAD), .I(MASTEREN));
//synthesis attribute LOC of MASTEREN_PAD is "R3"
//synthesis attribute IOSTANDARD of MASTEREN_BUF is "LVTTL"
//synthesis attribute DRIVE of MASTEREN_BUF is "12"
//synthesis attribute SLEW of MASTEREN_BUF is "FAST"

OBUF ADDRESSDIR_BUF(.O(ADDRESSDIR_PAD), .I(ADDRESSDIR));
//synthesis attribute LOC of ADDRESSDIR_PAD is "Y4"
//synthesis attribute IOSTANDARD of ADDRESSDIR_BUF is "LVTTL"
//synthesis attribute DRIVE of ADDRESSDIR_BUF is "24"
//synthesis attribute SLEW of ADDRESSDIR_BUF is "FAST"

OBUF CTRLDIR_BUF(.O(CTRLDIR_PAD), .I(CTRLDIR));
//synthesis attribute LOC of CTRLDIR_PAD is "V3"
//synthesis attribute IOSTANDARD of CTRLDIR_BUF is "LVTTL"
//synthesis attribute DRIVE of CTRLDIR_BUF is "24"
//synthesis attribute SLEW of CTRLDIR_BUF is "FAST"

OBUF DATADIRH_BUF(.O(DATADIRH_PAD), .I(DATADIRH));
//synthesis attribute LOC of DATADIRH_PAD is "R18"
//synthesis attribute IOSTANDARD of DATADIRH_BUF is "LVTTL"
//synthesis attribute DRIVE of DATADIRH_BUF is "24"
//synthesis attribute SLEW of DATADIRH_BUF is "FAST"

OBUF DATADIRL_BUF(.O(DATADIRL_PAD), .I(DATADIRL));
//synthesis attribute LOC of DATADIRL_PAD is "R19"
//synthesis attribute IOSTANDARD of DATADIRL_BUF is "LVTTL"
//synthesis attribute DRIVE of DATADIRL_BUF is "24"
//synthesis attribute SLEW of DATADIRL_BUF is "FAST"


//-----------Databus-----------//
IOBUF D0_BUF(.IO(D_PAD0), .O(DIN[0]), .I(DOUT[0]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD0 is "T17"
//synthesis attribute IOSTANDARD of D0_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD0 is "TRUE"
//synthesis attribute DRIVE of D0_BUF is "12"
//synthesis attribute SLEW of D0_BUF is "FAST"

IOBUF D1_BUF(.IO(D_PAD1), .O(DIN[1]), .I(DOUT[1]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD1 is "T18"
//synthesis attribute IOSTANDARD of D1_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD1 is "TRUE"
//synthesis attribute DRIVE of D1_BUF is "12"
//synthesis attribute SLEW of D1_BUF is "FAST"

IOBUF D2_BUF(.IO(D_PAD2), .O(DIN[2]), .I(DOUT[2]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD2 is "U18"
//synthesis attribute IOSTANDARD of D2_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD2 is "TRUE"
//synthesis attribute DRIVE of D2_BUF is "12"
//synthesis attribute SLEW of D2_BUF is "FAST"

IOBUF D3_BUF(.IO(D_PAD3), .O(DIN[3]), .I(DOUT[3]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD3 is "R20"
//synthesis attribute IOSTANDARD of D3_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD3 is "TRUE"
//synthesis attribute DRIVE of D3_BUF is "12"
//synthesis attribute SLEW of D3_BUF is "FAST"

IOBUF D4_BUF(.IO(D_PAD4), .O(DIN[4]), .I(DOUT[4]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD4 is "V19"
//synthesis attribute IOSTANDARD of D4_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD4 is "TRUE"
//synthesis attribute DRIVE of D4_BUF is "12"
//synthesis attribute SLEW of D4_BUF is "FAST"

IOBUF D5_BUF(.IO(D_PAD5), .O(DIN[5]), .I(DOUT[5]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD5 is "T20"
//synthesis attribute IOSTANDARD of D5_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD5 is "TRUE"
//synthesis attribute DRIVE of D5_BUF is "12"
//synthesis attribute SLEW of D5_BUF is "FAST"

IOBUF D6_BUF(.IO(D_PAD6), .O(DIN[6]), .I(DOUT[6]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD6 is "U17"
//synthesis attribute IOSTANDARD of D6_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD6 is "TRUE"
//synthesis attribute DRIVE of D6_BUF is "12"
//synthesis attribute SLEW of D6_BUF is "FAST"

IOBUF D7_BUF(.IO(D_PAD7), .O(DIN[7]), .I(DOUT[7]), .T(DATATRISL));
//synthesis attribute LOC of D_PAD7 is "T19"
//synthesis attribute IOSTANDARD of D7_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD7 is "TRUE"
//synthesis attribute DRIVE of D7_BUF is "12"
//synthesis attribute SLEW of D7_BUF is "FAST"

IOBUF D8_BUF(.IO(D_PAD8), .O(DIN[8]), .I(DOUT[8]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD8 is "U19"
//synthesis attribute IOSTANDARD of D8_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD8 is "TRUE"
//synthesis attribute DRIVE of D8_BUF is "12"
//synthesis attribute SLEW of D8_BUF is "FAST"

IOBUF D9_BUF(.IO(D_PAD9), .O(DIN[9]), .I(DOUT[9]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD9 is "V18"
//synthesis attribute IOSTANDARD of D9_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD9 is "TRUE"
//synthesis attribute DRIVE of D9_BUF is "12"
//synthesis attribute SLEW of D9_BUF is "FAST"

IOBUF D10_BUF(.IO(D_PAD10), .O(DIN[10]), .I(DOUT[10]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD10 is "V17"
//synthesis attribute IOSTANDARD of D10_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD10 is "TRUE"
//synthesis attribute DRIVE of D10_BUF is "12"
//synthesis attribute SLEW of D10_BUF is "FAST"

IOBUF D11_BUF(.IO(D_PAD11), .O(DIN[11]), .I(DOUT[11]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD11 is "W17"
//synthesis attribute IOSTANDARD of D11_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD11 is "TRUE"
//synthesis attribute DRIVE of D11_BUF is "12"
//synthesis attribute SLEW of D11_BUF is "FAST"

IOBUF D12_BUF(.IO(D_PAD12), .O(DIN[12]), .I(DOUT[12]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD12 is "Y17"
//synthesis attribute IOSTANDARD of D12_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD12 is "TRUE"
//synthesis attribute DRIVE of D12_BUF is "12"
//synthesis attribute SLEW of D12_BUF is "FAST"

IOBUF D13_BUF(.IO(D_PAD13), .O(DIN[13]), .I(DOUT[13]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD13 is "W19"
//synthesis attribute IOSTANDARD of D13_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD13 is "TRUE"
//synthesis attribute DRIVE of D13_BUF is "12"
//synthesis attribute SLEW of D13_BUF is "FAST"

IOBUF D14_BUF(.IO(D_PAD14), .O(DIN[14]), .I(DOUT[14]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD14 is "V20"
//synthesis attribute IOSTANDARD of D14_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD14 is "TRUE"
//synthesis attribute DRIVE of D14_BUF is "12"
//synthesis attribute SLEW of D14_BUF is "FAST"

IOBUF D15_BUF(.IO(D_PAD15), .O(DIN[15]), .I(DOUT[15]), .T(DATATRISH));
//synthesis attribute LOC of D_PAD15 is "W18"
//synthesis attribute IOSTANDARD of D15_BUF is "LVTTL"
//synthesis attribute PULLDOWN of D_PAD15 is "TRUE"
//synthesis attribute DRIVE of D15_BUF is "12"
//synthesis attribute SLEW of D_15_BUF is "FAST"


//----------Address Bus-----------//
IOBUF A0_BUF(.IO(A_PAD0), .O(A[0]), .I(A_IN[0]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD0 is "R2"
//synthesis attribute IOSTANDARD of A0_BUF is "LVTTL"
//synthesis attribute DRIVE of A0_BUF is "12"
//synthesis attribute SLEW of A0_BUF is "FAST"

IOBUF A1_BUF(.IO(A_PAD1), .O(A[1]), .I(A_IN[1]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD1 is "U2"
//synthesis attribute IOSTANDARD of A1_BUF is "LVTTL"
//synthesis attribute DRIVE of A1_BUF is "12"
//synthesis attribute SLEW of A1_BUF is "FAST"

IOBUF A2_BUF(.IO(A_PAD2), .O(A[2]), .I(A_IN[2]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD2 is "V1"
//synthesis attribute IOSTANDARD of A2_BUF is "LVTTL"
//synthesis attribute DRIVE of A2_BUF is "12"
//synthesis attribute SLEW of A2_BUF is "FAST"

IOBUF A3_BUF(.IO(A_PAD3), .O(A[3]), .I(A_IN[3]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD3 is "W2"
//synthesis attribute IOSTANDARD of A3_BUF is "LVTTL"
//synthesis attribute DRIVE of A3_BUF "12"
//synthesis attribute SLEW of A3_BUF is "FAST"

IOBUF A4_BUF(.IO(A_PAD4), .O(A[4]), .I(A_IN[4]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD4 is "T1"
//synthesis attribute IOSTANDARD of A4_BUF is "LVTTL"
//synthesis attribute DRIVE of A4_BUF is "12"
//synthesis attribute SLEW of A4_BUF is "FAST"

IOBUF A5_BUF(.IO(A_PAD5), .O(A[5]), .I(A_IN[5]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD5 is "R1"
//synthesis attribute IOSTANDARD of A5_BUF is "LVTTL"
//synthesis attribute DRIVE of A5_BUF is "12"
//synthesis attribute SLEW of A5_BUF is "FAST"

IOBUF A6_BUF(.IO(A_PAD6), .O(A[6]), .I(A_IN[6]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD6 is "T4"
//synthesis attribute IOSTANDARD of A6_BUF is "LVTTL"
//synthesis attribute DRIVE of A6_BUF is "12"
//synthesis attribute SLEW of A6_BUF is "FAST"

IOBUF A7_BUF(.IO(A_PAD7), .O(A[7]), .I(A_IN[7]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD7 is "T3"
//synthesis attribute IOSTANDARD of A7_BUF is "LVTTL"
//synthesis attribute DRIVE of A7_BUF is "12"
//synthesis attribute SLEW of A7_BUF is "FAST"

IOBUF A8_BUF(.IO(A_PAD8), .O(A[8]), .I(A_IN[8]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD8 is "W4"
//synthesis attribute IOSTANDARD of A8_BUF is "LVTTL"
//synthesis attribute DRIVE of A8_BUF is "12"
//synthesis attribute SLEW of A8_BUF is "FAST"

IOBUF A9_BUF(.IO(A_PAD9), .O(A[9]), .I(A_IN[9]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD9 is "U6"
//synthesis attribute IOSTANDARD of A9_BUF is "LVTTL"
//synthesis attribute DRIVE of A9_BUF is "12"
//synthesis attribute SLEW of A9_BUF is "FAST"

IOBUF A10_BUF(.IO(A_PAD10), .O(A[10]), .I(A_IN[10]), .T(nADDRESSDIR));
//synthesis attribute LOC of A_PAD10 is "W5"
//synthesis attribute IOSTANDARD of A10_BUF is "LVTTL"
//synthesis attribute DRIVE of A10_BUF is "12"
//synthesis attribute SLEW of A10_BUF is "FAST"



//-----------Flash ROM-------------//
OBUF FLASH_CE_BUF(.O(FLASH_CE_PAD), .I(FLASH_CE));
//synthesis attribute LOC of FLASH_CE_PAD is "N17"
//synthesis attribute IOSTANDARD of FLASH_CE_BUF is "LVCMOS25"
//synthesis attribute DRIVE of FLASH_CE_BUF is "12"


OBUF FLASH_OE_BUF(.O(FLASH_OE_PAD), .I(FLASH_OE));
//synthesis attribute LOC of FLASH_OE_PAD is "M18"
//synthesis attribute IOSTANDARD of FLASH_OE_BUF is "LVCMOS25"
//synthesis attribute DRIVE of FLASH_OE_BUF is "12"

OBUF FLASH_WE_BUF(.O(FLASH_WE_PAD), .I(FLASH_WE));
//synthesis attribute LOC of FLASH_WE_PAD is "D18"
//synthesis attribute IOSTANDARD of FLASH_WE_BUF is "LVCMOS25"
//synthesis attribute DRIVE of FLASH_WE_BUF is "12"

OBUF FLASH_WP_BUF(.O(FLASH_WP_PAD), .I(FLASH_WP));
//synthesis attribute LOC of FLASH_WP_PAD is "A18"
//synthesis attribute IOSTANDARD of FLASH_WP_BUF is "LVCMOS25"
//synthesis attribute DRIVE of FLASH_WP_BUF is "12"

OBUF FLASH_RESET_BUF(.O(FLASH_RESET_PAD), .I(FLASH_RESET));
//synthesis attribute LOC of FLASH_RESET_PAD is "B19"
//synthesis attribute IOSTANDARD of FLASH_RESET_BUF is "LVCMOS25"
//synthesis attribute DRIVE of FLASH_RESET_BUF is "12"

OBUF FLASH_BYTE_BUF(.O(FLASH_BYTE_PAD), .I(FLASH_BYTE));
//synthesis attribute LOC of FLASH_BYTE_PAD is "G20"
//synthesis attribute IOSTANDARD of FLASH_BYTE_BUF is "LVCMOS25"
//synthesis attribute DRIVE of FLASH_BYTE_BUF is "12"


IBUF FLASH_BUSY_BUF(.I(FLASH_BUSY_PAD), .O(FLASH_BUSY));
//synthesis attribute LOC of FLASH_BUSY_PAD is "C18"
//synthesis attribute IOSTANDARD of FLASH_BUSY_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASH_BUSY_PAD is "TRUE"


IOBUF FLASHD0_BUF(.IO(FLASHD_PAD0), .O(FLASH_DIN[0]), .I(FLASH_DOUT[0]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD0 is "U9"
//synthesis attribute IOSTANDARD of FLASHD0_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD0 is "TRUE"
//synthesis attribute DRIVE of FLASHD0_BUF is "12"

IOBUF FLASHD1_BUF(.IO(FLASHD_PAD1), .O(FLASH_DIN[1]), .I(FLASH_DOUT[1]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD1 is "V10"
//synthesis attribute IOSTANDARD of FLASHD1_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD1 is "TRUE"
//synthesis attribute DRIVE of FLASHD1_BUF is "12"

IOBUF FLASHD2_BUF(.IO(FLASHD_PAD2), .O(FLASH_DIN[2]), .I(FLASH_DOUT[2]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD2 is "V11"
//synthesis attribute IOSTANDARD of FLASHD2_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD2 is "TRUE"
//synthesis attribute DRIVE of FLASHD2_BUF is "12"

IOBUF FLASHD3_BUF(.IO(FLASHD_PAD3), .O(FLASH_DIN[3]), .I(FLASH_DOUT[3]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD3 is "U12"
//synthesis attribute IOSTANDARD of FLASHD3_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD3 is "TRUE"
//synthesis attribute DRIVE of FLASHD3_BUF is "12"

IOBUF FLASHD4_BUF(.IO(FLASHD_PAD4), .O(FLASH_DIN[4]), .I(FLASH_DOUT[4]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD4 is "V8"
//synthesis attribute IOSTANDARD of FLASHD4_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD4 is "TRUE"
//synthesis attribute DRIVE of FLASHD4_BUF is "12"

IOBUF FLASHD5_BUF(.IO(FLASHD_PAD5), .O(FLASH_DIN[5]), .I(FLASH_DOUT[5]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD5 is "V9"
//synthesis attribute IOSTANDARD of FLASHD5_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD5 is "TRUE"
//synthesis attribute DRIVE of FLASHD5_BUF is "12"

IOBUF FLASHD6_BUF(.IO(FLASHD_PAD6), .O(FLASH_DIN[6]), .I(FLASH_DOUT[6]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD6 is "V12"
//synthesis attribute IOSTANDARD of FLASHD6_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD6 is "TRUE"
//synthesis attribute DRIVE of FLASHD6_BUF is "12"

IOBUF FLASHD7_BUF(.IO(FLASHD_PAD7), .O(FLASH_DIN[7]), .I(FLASH_DOUT[7]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD7 is "V13"
//synthesis attribute IOSTANDARD of FLASHD7_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD7 is "TRUE"
//synthesis attribute DRIVE of FLASHD7_BUF is "12"

IOBUF FLASHD8_BUF(.IO(FLASHD_PAD8), .O(FLASH_DIN[8]), .I(FLASH_DOUT[8]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD8 is "M19"
//synthesis attribute IOSTANDARD of FLASHD8_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD8 is "TRUE"
//synthesis attribute DRIVE of FLASHD8_BUF is "12"

IOBUF FLASHD9_BUF(.IO(FLASHD_PAD9), .O(FLASH_DIN[9]), .I(FLASH_DOUT[9]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD9 is "M17"
//synthesis attribute IOSTANDARD of FLASHD9_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD9 is "TRUE"
//synthesis attribute DRIVE of FLASHD9_BUF is "12"

IOBUF FLASHD10_BUF(.IO(FLASHD_PAD10), .O(FLASH_DIN[10]), .I(FLASH_DOUT[10]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD10 is "P17"
//synthesis attribute IOSTANDARD of FLASHD10_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD10 is "TRUE"
//synthesis attribute DRIVE of FLASHD10_BUF is "12"

IOBUF FLASHD11_BUF(.IO(FLASHD_PAD11), .O(FLASH_DIN[11]), .I(FLASH_DOUT[11]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD11 is "L17"
//synthesis attribute IOSTANDARD of FLASHD11_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD11 is "TRUE"
//synthesis attribute DRIVE of FLASHD11_BUF is "12"

IOBUF FLASHD12_BUF(.IO(FLASHD_PAD12), .O(FLASH_DIN[12]), .I(FLASH_DOUT[12]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD12 is "J18"
//synthesis attribute IOSTANDARD of FLASHD12_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD12 is "TRUE"
//synthesis attribute DRIVE of FLASHD12_BUF is "12"

IOBUF FLASHD13_BUF(.IO(FLASHD_PAD13), .O(FLASH_DIN[13]), .I(FLASH_DOUT[13]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD13 is "K20"
//synthesis attribute IOSTANDARD of FLASHD13_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD13 is "TRUE"
//synthesis attribute DRIVE of FLASHD13_BUF is "12"

IOBUF FLASHD14_BUF(.IO(FLASHD_PAD14), .O(FLASH_DIN[14]), .I(FLASH_DOUT[14]), .T(FLASH_TRIS_D));
//synthesis attribute LOC of FLASHD_PAD14 is "F20"                                        
//synthesis attribute IOSTANDARD of FLASHD14_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD14 is "TRUE"
//synthesis attribute DRIVE of FLASHD14_BUF is "12"


//This trickery is for running the flash in 8 bit mode
wire FLASH_DOUT15_MUX = (~FLASH_BYTE)?FLASH_AOUT_NEG_ONE : FLASH_DOUT[15];
IOBUF FLASHD15_BUF(.IO(FLASHD_PAD15), .O(FLASH_DIN[15]), .I(FLASH_DOUT15_MUX), .T(FLASH_TRIS_D15));
//synthesis attribute LOC of FLASHD_PAD15 is "L19"
//synthesis attribute IOSTANDARD of FLASHD15_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of FLASHD_PAD15 is "TRUE"
//synthesis attribute DRIVE of FLASHD15_BUF is "12"

IOBUF FLASHA0_BUF(.IO(FLASHA_PAD0), .O(FLASH_AIN[0]), .I(FLASH_AOUT[0]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD0 is "N18"
//synthesis attribute IOSTANDARD of FLASHA0_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD0 is "TRUE"
//synthesis attribute DRIVE of FLASHA0_BUF is "12"

IOBUF FLASHA1_BUF(.IO(FLASHA_PAD1), .O(FLASH_AIN[1]), .I(FLASH_AOUT[1]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD1 is "P19"
//synthesis attribute IOSTANDARD of FLASHA1_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD1 is "TRUE"
//synthesis attribute DRIVE of FLASHA1_BUF is "12"

IOBUF FLASHA2_BUF(.IO(FLASHA_PAD2), .O(FLASH_AIN[2]), .I(FLASH_AOUT[2]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD2 is "K18"
//synthesis attribute IOSTANDARD of FLASHA2_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD2 is "TRUE"
//synthesis attribute DRIVE of FLASHA2_BUF is "12"

IOBUF FLASHA3_BUF(.IO(FLASHA_PAD3), .O(FLASH_AIN[3]), .I(FLASH_AOUT[3]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD3 is "J17"
//synthesis attribute IOSTANDARD of FLASHA3_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD3 is "TRUE"
//synthesis attribute DRIVE of FLASHA3_BUF is "12"

IOBUF FLASHA4_BUF(.IO(FLASHA_PAD4), .O(FLASH_AIN[4]), .I(FLASH_AOUT[4]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD4 is "J19"
//synthesis attribute IOSTANDARD of FLASHA4_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD4 is "TRUE"
//synthesis attribute DRIVE of FLASHA4_BUF is "12"

IOBUF FLASHA5_BUF(.IO(FLASHA_PAD5), .O(FLASH_AIN[5]), .I(FLASH_AOUT[5]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD5 is "K19"
//synthesis attribute IOSTANDARD of FLASHA5_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD5 is "TRUE"
//synthesis attribute DRIVE of FLASHA5_BUF is "12"

IOBUF FLASHA6_BUF(.IO(FLASHA_PAD6), .O(FLASH_AIN[6]), .I(FLASH_AOUT[6]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD6 is "K17"
//synthesis attribute IOSTANDARD of FLASHA6_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD6 is "TRUE"
//synthesis attribute DRIVE of FLASHA6_BUF is "12"

IOBUF FLASHA7_BUF(.IO(FLASHA_PAD7), .O(FLASH_AIN[7]), .I(FLASH_AOUT[7]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD7 is "G19"
//synthesis attribute IOSTANDARD of FLASHA7_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD7 is "TRUE"
//synthesis attribute DRIVE of FLASHA7_BUF is "12"

IOBUF FLASHA8_BUF(.IO(FLASHA_PAD8), .O(FLASH_AIN[8]), .I(FLASH_AOUT[8]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD8 is "D17"
//synthesis attribute IOSTANDARD of FLASHA8_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD8 is "TRUE"
//synthesis attribute DRIVE of FLASHA8_BUF is "12"

IOBUF FLASHA9_BUF(.IO(FLASHA_PAD9), .O(FLASH_AIN[9]), .I(FLASH_AOUT[9]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD9 is "B18"
//synthesis attribute IOSTANDARD of FLASHA9_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD9 is "TRUE"
//synthesis attribute DRIVE of FLASHA9_BUF is "12"

IOBUF FLASHA10_BUF(.IO(FLASHA_PAD10), .O(FLASH_AIN[10]), .I(FLASH_AOUT[10]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD10 is "E19"
//synthesis attribute IOSTANDARD of FLASHA10_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD10 is "TRUE"
//synthesis attribute DRIVE of FLASHA10_BUF is "12"

IOBUF FLASHA11_BUF(.IO(FLASHA_PAD11), .O(FLASH_AIN[11]), .I(FLASH_AOUT[11]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD11 is "F18"
//synthesis attribute IOSTANDARD of FLASHA11_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD11 is "TRUE"
//synthesis attribute DRIVE of FLASHA11_BUF is "12"

IOBUF FLASHA12_BUF(.IO(FLASHA_PAD12), .O(FLASH_AIN[12]), .I(FLASH_AOUT[12]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD12 is "F17"
//synthesis attribute IOSTANDARD of FLASHA12_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD12 is "TRUE"
//synthesis attribute DRIVE of FLASHA12_BUF is "12"

IOBUF FLASHA13_BUF(.IO(FLASHA_PAD13), .O(FLASH_AIN[13]), .I(FLASH_AOUT[13]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD13 is "C17"
//synthesis attribute IOSTANDARD of FLASHA13_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD13 is "TRUE"
//synthesis attribute DRIVE of FLASHA13_BUF is "12"

IOBUF FLASHA14_BUF(.IO(FLASHA_PAD14), .O(FLASH_AIN[14]), .I(FLASH_AOUT[14]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD14 is "D19"
//synthesis attribute IOSTANDARD of FLASHA14_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD14 is "TRUE"
//synthesis attribute DRIVE of FLASHA14_BUF is "12"

IOBUF FLASHA15_BUF(.IO(FLASHA_PAD15), .O(FLASH_AIN[15]), .I(FLASH_AOUT[15]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD15 is "G17"
//synthesis attribute IOSTANDARD of FLASHA15_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD15 is "TRUE"
//synthesis attribute DRIVE of FLASHA15_BUF is "12"

IOBUF FLASHA16_BUF(.IO(FLASHA_PAD16), .O(FLASH_AIN[16]), .I(FLASH_AOUT[16]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD16 is "E20"
//synthesis attribute IOSTANDARD of FLASHA16_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD16 is "TRUE"
//synthesis attribute DRIVE of FLASHA16_BUF is "12"

IOBUF FLASHA17_BUF(.IO(FLASHA_PAD17), .O(FLASH_AIN[17]), .I(FLASH_AOUT[17]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD17 is "H19"
//synthesis attribute IOSTANDARD of FLASHA17_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD17 is "TRUE"
//synthesis attribute DRIVE of FLASHA17_BUF is "12"

IOBUF FLASHA18_BUF(.IO(FLASHA_PAD18), .O(FLASH_AIN[18]), .I(FLASH_AOUT[18]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD18 is "H18"
//synthesis attribute IOSTANDARD of FLASHA18_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD18 is "TRUE"
//synthesis attribute DRIVE of FLASHA18_BUF is "12"

IOBUF FLASHA19_BUF(.IO(FLASHA_PAD19), .O(FLASH_AIN[19]), .I(FLASH_AOUT[19]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD19 is "F19"
//synthesis attribute IOSTANDARD of FLASHA19_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD19 is "TRUE"
//synthesis attribute DRIVE of FLASHA19_BUF is "12"

IOBUF FLASHA20_BUF(.IO(FLASHA_PAD20), .O(FLASH_AIN[20]), .I(FLASH_AOUT[20]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD20 is "H17"
//synthesis attribute IOSTANDARD of FLASHA20_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD20 is "TRUE"
//synthesis attribute DRIVE of FLASHA20_BUF is "12"

IOBUF FLASHA21_BUF(.IO(FLASHA_PAD21), .O(FLASH_AIN[21]), .I(FLASH_AOUT[21]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD21 is "E18"
//synthesis attribute IOSTANDARD of FLASHA21_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD21 is "TRUE"
//synthesis attribute DRIVE of FLASHA21_BUF is "12"

IOBUF FLASHA22_BUF(.IO(FLASHA_PAD22), .O(FLASH_AIN[22]), .I(FLASH_AOUT[22]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD22 is "C19"
//synthesis attribute IOSTANDARD of FLASHA22_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD22 is "TRUE"
//synthesis attribute DRIVE of FLASHA22_BUF is "12"

IOBUF FLASHA23_BUF(.IO(FLASHA_PAD23), .O(FLASH_AIN[23]), .I(FLASH_AOUT[23]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD23 is "C20"
//synthesis attribute IOSTANDARD of FLASHA23_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD23 is "TRUE"
//synthesis attribute DRIVE of FLASHA23_BUF is "12"

IOBUF FLASHA24_BUF(.IO(FLASHA_PAD24), .O(FLASH_AIN[24]), .I(FLASH_AOUT[24]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD24 is "H20"
//synthesis attribute IOSTANDARD of FLASHA24_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD24 is "TRUE"
//synthesis attribute DRIVE of FLASHA24_BUF is "12"

IOBUF FLASHA25_BUF(.IO(FLASHA_PAD25), .O(FLASH_AIN[25]), .I(FLASH_AOUT[25]), .T(FLASH_TRIS_A));
//synthesis attribute LOC of FLASHA_PAD25 is "L20"
//synthesis attribute IOSTANDARD of FLASHA25_BUF is "LVCMOS25"
//synthesis attribute PULLUP of FLASHA_PAD25 is "TRUE"
//synthesis attribute DRIVE of FLASHA25_BUF is "12"

//-----------TurboLoader-------------//
OBUF CPLD_PEEKABOO_BUF(.O(CPLD_PEEKABOO_PAD), .I(CPLD_PEEKABOO));
//synthesis attribute LOC of CPLD_PEEKABOO_PAD is "M20"
//synthesis attribute IOSTANDARD of CPLD_PEEKABOO_BUF is "LVCMOS25"
//synthesis attribute DRIVE of CPLD_PEEKABOO_BUF is "12"

OBUF CPLD_RELOAD_BUF(.O(CPLD_RELOAD_PAD), .I(CPLD_RELOAD));
//synthesis attribute LOC of CPLD_RELOAD_PAD is "P20"
//synthesis attribute IOSTANDARD of CPLD_RELOAD_BUF is "LVCMOS25"
//synthesis attribute DRIVE of CPLD_RELOAD_BUF is "12"

//------Internal JTAG Loopback-------//

OBUF JTAG_LOOPBACK_TCK_BUF(.O(JTAG_LOOPBACK_TCK_PAD), .I(JTAG_LOOPBACK_TCK));
//synthesis attribute LOC of JTAG_LOOPBACK_TCK_PAD is "D12"
//synthesis attribute IOSTANDARD of JTAG_LOOPBACK_TCK_BUF is "LVCMOS25"
//synthesis attribute DRIVE of JTAG_LOOPBACK_TCK_BUF is "12"

OBUF JTAG_LOOPBACK_TDI_BUF(.O(JTAG_LOOPBACK_TDI_PAD), .I(JTAG_LOOPBACK_TDI));
//synthesis attribute LOC of JTAG_LOOPBACK_TDI_PAD is "B12"
//synthesis attribute IOSTANDARD of JTAG_LOOPBACK_TDI_BUF is "LVCMOS25"
//synthesis attribute DRIVE of JTAG_LOOPBACK_TDI_BUF is "12" 

OBUF JTAG_LOOPBACK_TMS_BUF(.O(JTAG_LOOPBACK_TMS_PAD), .I(JTAG_LOOPBACK_TMS));
//synthesis attribute LOC of JTAG_LOOPBACK_TMS_PAD is "C16"
//synthesis attribute IOSTANDARD of JTAG_LOOPBACK_TMS_BUF is "LVCMOS25"
//synthesis attribute DRIVE of JTAG_LOOPBACK_TMS_BUF is "12" 

IBUF JTAG_LOOPBACK_TDO_BUF(.I(JTAG_LOOPBACK_TDO_PAD), .O(JTAG_LOOPBACK_TDO));
//synthesis attribute LOC of JTAG_LOOPBACK_TDO_PAD is "D13"
//synthesis attribute IOSTANDARD of JTAG_LOOPBACK_TDO_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of JTAG_LOOPBACK_TDO_PAD is "TRUE"


//--------General Purpose IO---------//

`ifdef ENABLE_GPIO_PADS
IOBUF GPIO_BUF1(.IO(GPIO_PAD1), .O(GPIO_IN[1]), .I(GPIO_OUT[1]), .T(GPIO_TRIS[1]));
//synthesis attribute LOC of GPIO_PAD1 is "B17"
//synthesis attribute IOSTANDARD of GPIO1_BUF is "LVCMOS25"
//synthesis attribute PULLUP of GPIO_PAD1 is "FALSE"
//synthesis attribute DRIVE of GPIO_BUF1 is "12"
//synthesis attribute SLEW of GPIO_BUF1 is "FAST"

IOBUF GPIO_BUF2(.IO(GPIO_PAD2), .O(GPIO_IN[2]), .I(GPIO_OUT[2]), .T(GPIO_TRIS[2]));
//synthesis attribute LOC of GPIO_PAD2 is "A16"
//synthesis attribute IOSTANDARD of GPIO2_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of GPIO_PAD2 is "FALSE"
//synthesis attribute DRIVE of GPIO_BUF2 is "12"
//synthesis attribute SLEW of GPIO_BUF2 is "FAST"

IOBUF GPIO_BUF3(.IO(GPIO_PAD3), .O(GPIO_IN[3]), .I(GPIO_OUT[3]), .T(GPIO_TRIS[3]));
//synthesis attribute LOC of GPIO_PAD3 is "B16"
//synthesis attribute IOSTANDARD of GPIO3_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of GPIO_PAD3 is "FALSE"
//synthesis attribute DRIVE of GPIO_BUF3 is "12"
//synthesis attribute SLEW of GPIO_BUF3 is "FAST"

IOBUF GPIO_BUF4(.IO(GPIO_PAD4), .O(GPIO_IN[4]), .I(GPIO_OUT[4]), .T(GPIO_TRIS[4]));
//synthesis attribute LOC of GPIO_PAD4 is "A15"
//synthesis attribute IOSTANDARD of GPIO4_BUF is "LVCMOS25"
//synthesis attribute PULLDOWN of GPIO_PAD4 is "FALSE"
//synthesis attribute DRIVE of GPIO_BUF4 is "12"
//synthesis attribute SLEW of GPIO_BUF4 is "FAST"
`endif


//------------10/100/1000 Ethernet Interface------------//
`ifdef ENABLE_MDIO_LOW_LEVEL
reg CLOCK1_DIV2;
always @(posedge CLOCK1) CLOCK1_DIV2 = ~CLOCK1_DIV2;
OBUF ETHER_25MHZ_BUF(.I(CLOCK1_DIV2), .O(ETHER_25MHZ_PAD));
//synthesis attribute LOC of ETHER_25MHZ_PAD is "F3"
//synthesis attribute IOSTANDARD of ETHER_25MHZ_BUF is "LVCMOS25"
//synthesis attribute SLEW of ETHER_25MHZ_PAD is "FAST"

IOBUF ETHER_MDIO_BUF(.IO(ETHER_MDIO_PAD), .I(ETHER_MDIO_O), .O(ETHER_MDIO_I), .T(ETHER_MDIO_T));
//synthesis attribute LOC of ETHER_MDIO_PAD is "B2"
//synthesis attribute IOSTANDARD of ETHER_MDIO_BUF is "LVCMOS25"

OBUF ETHER_MDC_BUF(.I(ETHER_MDC), .O(ETHER_MDC_PAD));
//synthesis attribute LOC of ETHER_MDC_PAD is "C2"
//synthesis attribute IOSTANDARD of ETHER_MDC_BUF is "LVCMOS25"

OBUF ETHER_RESET_BUF(.I(ETHER_RESET), .O(ETHER_RESET_PAD));
//synthesis attribute LOC of ETHER_RESET_PAD is "D2"
//synthesis attribute IOSTANDARD of ETHER_RESET_BUF is "LVCMOS25"

OBUF ETHER_COMA_BUF(.I(ETHER_COMA), .O(ETHER_COMA_PAD));
//synthesis attribute LOC of ETHER_COMA_PAD is "C1"
//synthesis attribute IOSTANDARD of ETHER_COMA_BUF is "LVCMOS25"
`endif //ENABLE_MDIO
